The invention relates to the field of floating gate devices on Silicon On Insulator (SOI).
General
Electronic devices perform several functions, including digital, analog and memory. Memory devices fall into two broad categories: volatile and non-volatile, with the distinction that volatile memory loses its information when power is removed while non-volatile memory does not.
Multiple types of non-volatile (NV) memory have been used over the years, with the most common based on magnetic devices such as magnetic core, tape or discs or optical devices such as CD-ROM. Such devices offer high density and low cost, but cannot be integrated onto integrated circuits. They are therefore typically used in computer systems as separate modules, but cannot provide non-volatile memory as an integral part of an integrated circuit, or chip.
Including non-volatile storage of information on board a chip has become increasingly important. With such capability, standard chips can be permanently programmed to perform specialized functions; variable coefficients can be permanently stored; and critical data can be backed up during operation to improve system reliability. Additionally, on-chip NV memory enables a single chip to be manufactured in large volume for multiple markets, with customization provided by programming, either at the manufacturer or by the customer. This provides cost efficiency from the large volume production to lower volume, customized applications. NV memory is particularly important for battery operated systems such as cellular phones and portable consumer electronics where both customization and information storage is required and must survive complete loss of power.
Uses of on-chip NV memory continue to expand with its availability. Many wireless systems require significant permanent customization to set radio performance specifications (e.g., frequency plans, gain levels, internal operating conditions, A/D performance, account information, security codes and software changes or upgrades). New markets include so-called IC cards used as credit cards, pre-paid purchase cards, medical records storage and RF ID tags. Other new applications include content addressable memory, security verification, package tracking, commercial satellites and many more. The key to these new applications is to be able to include NV memory with as many other microelectronic functions as possible.
Storage Cells
The original NV memory was commonly called Floating-gate Avalanche-injection MOS (FAMOS) and is described in U.S. Pat. Nos. 3,500,142 and 3,919,711. In this device, a polysilicon gate transistor was made without electrical contact to the gate conductor. By applying a high voltage to the drain of an N-channel transistor, small currents were amplified through avalanche gain, creating high energy (or xe2x80x9chotxe2x80x9d) electrons or holes. The combination of high energy and large voltage on the drain forced some of the carriers to penetrate through the gate oxide and onto the electrically floating polysilicon gate conductor. Once charged, the gate maintained the transistor in a conducting, or xe2x80x9conxe2x80x9d, state which represented a stored bit of information. Initial products were based on bulk Si PMOS transistors storing electrons on the gate. However, no integrated electrical mechanism was available to inject electrons or to remove holes thereby providing an erase function.
While effective at writing, the lack of an electronic mechanism to erase or remove the stored charge was a severe limitation. Hence, this class of device became known as an Electrically Programmable Read Only Memory, or EPROM. The erasing mechanism devised was to apply ultraviolet light which gave the stored charge sufficient energy to return to the silicon and be dissipated, hence the name UVEPROM. UV erasing was time consuming, required special equipment and device packaging and perhaps worst of all, it required removal of the device from the system for reprogramming. The value of NV memory was so great that these drawbacks did not prevent UVEPROM from becoming a very successful product. However, the drawbacks led to a search for a next generation of device, the Electrically Erasable PROM, called EEPROM or E2PROM and often referred to simply as E-squared. By providing electrically erasable memory, the UV light, special packaging and removal requirements were eliminated and NV memory became an industry segment unto itself, spawning numerous companies.
In EEPROM, a second polysilicon layer is placed above or near the floating storage node and separated by a very thin, high quality silicon dioxide layer, as described in many U.S. Patents, including U.S. Pat. Nos. 3,996,657, 5,587,947 and 5,689,459. Writing occurs by applying a drain source voltage of sufficient magnitude to create source-drain current with channel hot electrons (CHE) of sufficient energy and momentum to penetrate the gate oxide. Erasing occurs by applying a high voltage to the second gate, sufficiently high electric fields can be generated to induce the quantum mechanical tunneling phenomenon (Fowler-Nordheim), in which a charged particle penetrates a thin insulating layer. With the second gate, an electrical erasing mechanism is integrated onto the chip, thereby eliminating the need for UV light and more importantly, allowing in-system re-programming. However, process complexity increases and on-chip high voltages have to be generated, controlled and routed. The high electric field eventually causes damage to the thin oxide layer, creating reliability issues. Also, the erasing mechanism is an inherently unstable process which can cause over-erasing (and subsequent under-writing) and other problems. Sophisticated control circuits are required to ensure proper operation.
Multiple variations on the EEPROM writing and erasing mechanisms have been defined and used. Processing and layout details affect performance, speed and reliability. Control of the thin oxide layers must be to the highest standards, often limiting yield and manufacturability. Many large chips, such as high performance microprocessors and digital signal processors would benefit from inclusion of EEPROM, but the process and design complexity can make this prohibitively expensive. However, in specialized processing facilities, large NV memory chips known as Flash memory use a variation of EEPROM storage cells and are manufactured cost effectively.
A recent variation on the standard EEPROM cell is the so-called stepped channel device, as described in U.S. Pat. No. 5,780,341. In this cell, a shallow step is introduced into the channel region of the writing transistor, making the drain slightly lower than the source. As electrons transit from source to drain, they encounter the step. The step enhances CHE injection mechanism thereby completing the writing mechanism at lower voltage. The detailed mechanisms are described in the references, but can be thought of as a microscopic solid state electron implanter. By adjusting the size and location of the step along with the transistor design, electrons can be written effectively. However, this still leaves the requirement to erase the cell, which is done by conventional Fowler-Nordheim tunneling as found in conventional EEPROM.
Processes
EEPROM storage cells are inherently MOS devices and can be integrated into any MOS process. However, the high voltages necessary for programming add additional requirements to the process to deal with routing of the high voltage signals. In standard CMOS, regions between transistors are called the field and constitute a parasitic MOS transistor. If this region is improperly designed so-called field inversion can occur, thereby improperly shorting together two or more adjacent transistors. High voltage on interconnects increases this problem and forces changes to the CMOS process. Additionally, CMOS circuits can exhibit a phenomenon known as latch-up in which a large, stable current can be triggered which can either destroy the chip or at least force power down. Modern CMOS processes normally designed to handle 3 V or less must therefore be modified significantly to enable them to handle the high programming voltages if EEPROM cells are to be added. Additionally, transistors and other circuit elements (often called charge pump circuits) must be included to create and route the high voltage signals. These elements must themselves be designed to handle the high voltage and the silicon substrate must also be designed to deal with substrate currents induced by the signals. In short, adding EEPROM circuitry to standard CMOS requires a great deal of design and process technology which in turn increases complexity and cost. Even with the greatest care and effort, many companies have failed at creating cost effective EEPROM.
Since many of the problems associated with integrating EEPROM with standard CMOS arise from interactions with the Si substrate, an ideal process for this task is silicon on insulator, or SOI. SOI is a structure in which a silicon film is formed on an insulating layer or substrate. CMOS on SOI enables completely dielectric isolation of each transistor, thereby eliminating silicon laterally from the field regions and associated field inversion problems. The insulating layer below each transistor is also incapable of supporting substrate current, especially those created by high voltage circuitry and signals. Three US patents discuss EEPROM on SOI: 5,411,905; 5,455,791 and 5,886,376. In all three patents, a traditional Fowler-Nordheim mechanism is described based on a floating gate and a capacitively coupled control gate.
SOI structures also provide opportunities to use transistors in different ways, since source and drain junctions cannot be forward biased to the substrate. Such flexibility can permit circuit topologies not permitted in bulk Si CMOS. It also simplifies charge pump design.
Since its first invention, it has been recognized that a low voltage EEPROM cell manufactured without additional processing steps would be an ideal solution. With such a cell, NV memory could be integrated into virtually all CMOS circuitry by standard design techniques. Lower voltage operation would reduce the need for high voltage circuitry, and improve reliability of the thin oxide layer. The term low voltage means low compared to the traditional writing and erasing voltages of up to 19 V, as is currently common in the industry. It is desirable to have a minimum voltage for writing to the cell, at least above the voltages typically used to operate the rest of the chip""s circuitry. This is for the obvious reason that it provides protection against standard control signals inadvertently writing information into the storage cells.
An ideal cell would also be able to write and erase in a controlled, measurable fashion, thereby reducing the risk of over-erasing. The tunneling injection mechanisms currently used are exponentially non-linear forcing tight process and circuit controls to ensure proper writing and erasing. Finally, low voltage operation reduces power consumption and meets the constant need to reduce voltages of virtually all modern electronic systems.
SOI embodiments would have higher speed and some reduced high voltage sensitivity, but the basic logic and storage cells can be the same as those described for bulk Si. However, SOI offers a degree of freedom not available in bulk silicon: each transistor is electrically isolated from each other which enables a unique cell construction and erasing mechanism which provides the long-sought integratable EEPROM cell without additional processing layers.
These and other desirable characteristics are embodied in the present invention.
In a first aspect, the present invention is a semiconductor device comprising: an island of semiconductor material on an insulating substrate; a first electronic device of a first conductivity type fabricated in the island of semiconductor material, the first electronic device comprising: a first device source region; a first device drain region; and a first device channel region positioned between the first device source region and the first device drain region, wherein a portion of the first device channel region is a common channel region; and a second electronic device of a second conductivity type fabricated in the island of semiconductor material, the second electronic device comprising: a second device source region; a second device drain region; and a second device channel region positioned between the second device source region and the second device drain region, wherein a portion of the second device channel region includes the common channel region. The device may further include a common floating gate positioned over at least a portion of each of the first device channel region and the second device channel region, the common floating gate further comprising: a gate insulating layer positioned adjacent the common channel region; and a gate conductive layer positioned adjacent the gate insulating layer. In some configurations, the gate insulating layer may further comprise an oxide layer and the gate conductive layer may further comprise a polysilicon layer. In some configurations, the semiconductor device may further comprise an injector, the injector comprising a region wherein the common floating gate penetrates into the common channel region such that the injector is surrounded by the common channel region. In some configurations, the semiconductor device further comprises an Electrically Erasable Programmable Read Only Memory, called EEPROM, device. In some configurations, the semiconductor material further comprises silicon. In some configurations, the insulating substrate further comprises sapphire. In some configurations, the insulating substrate further comprises a layer of silicon dioxide.
In a second aspect, the present invention is a semiconductor device comprising: a first island of semiconductor material on an insulating substrate wherein the first island of semiconductor material further comprises: a first region and a second region of a first conductivity type separated by a first channel region positioned between the first and second regions; and a third region of a second conductivity type which is adjacent to the first channel region; a second island of semiconductor material on the insulating substrate wherein the second island of semiconductor material further comprises a fourth region and a fifth region of the first conductivity type separated by a second channel region positioned between the fourth and fifth regions; a third island of semiconductor material on the insulating substrate wherein the third island of semiconductor material further comprises: a sixth region and a seventh region of the first conductivity type separated by a third channel region positioned between the sixth and seventh regions; and an eighth region of the second conductivity type which is adjacent to the third channel region; and a floating gate common to the first, second and third channel regions, the common floating gate further comprising: a gate insulating layer positioned adjacent the first, second and third channel regions; and a gate conductive layer positioned adjacent the gate insulating layer. The device may further comprise an injector, the injector comprising a region wherein the common floating gate penetrates into at least one of the first, second or third channel regions. In some configurations, the semiconductor material further comprises silicon. In some configurations, the insulating substrate further comprises sapphire. In some configurations, the insulating substrate further comprises a layer of silicon dioxide.
In a third aspect, the present invention is a multiport semiconductor device comprising: an island of semiconductor material on an insulating substrate wherein the island of semiconductor material further comprises: a first region and a second region of a first conductivity type separated by a first channel region positioned between the first and second regions; a third region of a second conductivity type which is adjacent to the first channel region; a fourth region and a fifth region of the first conductivity type separated by a second channel region positioned between the fourth and fifth regions; a sixth region of the second conductivity type which is adjacent to the second channel region; and a floating gate common to the first and second channel regions. In some configurations, the common floating gate further comprises: a gate insulating layer positioned adjacent the first and second channel regions; and a gate conductive layer positioned adjacent the gate insulating layer. The device may further include an injector, the injector comprising a region wherein the common floating gate penetrates into at least one of the first or second channel regions. In some configurations, the semiconductor material further comprises silicon. In some configurations, the insulating substrate further comprises sapphire. In some configurations, the insulating substrate further comprises a layer of silicon dioxide.
In a fourth aspect, the present invention is an EEPROM cell with integrated inverter serving as a latching sense amplifier semiconductor device, the device comprising: an EEPROM cell formed on a first island of semiconductor material on an insulating substrate wherein the EEPROM cell further comprises: a first region and a second region of a first conductivity type separated by a first channel region positioned between the first and second regions; and a third region of a second conductivity type which is adjacent to the first channel region; an inverter configured as a latching sense amplifier comprising: a second island of semiconductor material on the insulating substrate wherein the second island of semiconductor material further comprises a fourth region and a fifth region of the first conductivity type separated by a second channel region positioned between the fourth and fifth regions; and a third island of semiconductor material on the insulating substrate wherein the third island of semiconductor material further comprises a sixth region and a seventh region of the second conductivity type separated by a third channel region positioned between the sixth and seventh regions, wherein a voltage Vss is applied to the fourth region of first conductivity type, a voltage Vdd is applied to the sixth region of second conductivity type, and the fifth region of first conductivity type and the seventh region of second conductivity type are interconnected as an output for the latching sense amplifier; and a floating gate common to the first, second and third channel regions. The device may further include an injector, the injector comprising a region wherein the common floating gate penetrates into one or more of the first, second or third channel regions. In some configurations, the semiconductor material further comprises silicon. In some configurations, the insulating substrate further comprises sapphire. In some configurations, the insulating substrate further comprises a layer of silicon dioxide.
In a fifth aspect, the present invention is an EEPROM cell with integrated NAND gate semiconductor device, the device comprising: a first EEPROM cell formed on a first island of semiconductor material on an insulating substrate wherein the first EEPROM cell further comprises: a first region and a second region of a first conductivity type separated by a first channel region positioned between the first and second regions; and a third region of a second conductivity type which is adjacent to the first channel region; a second EEPROM cell formed on a second island of semiconductor material on the insulating substrate wherein the second EEPROM cell further comprises: a fourth region and a fifth region of the first conductivity type separated by a second channel region positioned between the fourth and fifth regions; and a sixth region of the second conductivity type which is adjacent to the second channel region; a third island of semiconductor material on the insulating substrate wherein the third island of semiconductor material further comprises a seventh region, an eighth region and a ninth region of the first conductivity type wherein the seventh and eighth regions are separated by a third channel region positioned between the seventh and eighth regions and the eighth and ninth regions are separated by a fourth channel region positioned between the eighth and ninth regions; a fourth island of semiconductor material on the insulating substrate wherein the fourth island of semiconductor material further comprises a tenth region, an eleventh region and a twelfth region of the second conductivity type wherein the tenth and eleventh regions are separated by a fifth channel region positioned between the tenth and eleventh regions and the eleventh and twelfth regions are separated by a sixth channel region positioned between the eleventh and twelfth regions, wherein a voltage Vss is applied to the seventh region of first conductivity type, a voltage Vdd is applied to the tenth region of second conductivity type, and the ninth region of the first conductivity type and the eleventh region of the second conductivity type are interconnected as an output for a NAND logic function; a first floating gate common to the first, third and fifth channel regions; and a second floating gate common to the second, fourth and sixth channel regions. The device may further include at least one injector, the injector comprising a region wherein either one or both of the first common floating gate or the second common floating gate penetrates into the first or second channel region, respectively. In some configurations, the semiconductor material further comprises silicon. In some configurations, the insulating substrate further comprises sapphire. In some configurations, the insulating substrate further comprises a layer of silicon dioxide.
In a sixth aspect, the present invention is a semiconductor device comprising: an island of semiconductor material on an insulating substrate wherein the island of semiconductor material further comprises: a first region and a second region of a first conductivity type separated by a channel region positioned between the first and second regions; and a third region of a second conductivity type which is adjacent to the channel region; and a floating gate positioned over the channel region. The device may further include an injector, the injector comprising a region wherein the floating gate penetrates into the channel region. In some configurations, the semiconductor material further comprises silicon. In some configurations, the insulating substrate further comprises sapphire. In some configurations, the insulating substrate further comprises silicon dioxide.
In a seventh aspect, the present invention is a semiconductor programmable interconnect device, the device comprising: an EEPROM cell formed on an island of semiconductor material on an insulating substrate wherein the EEPROM cell further comprises: a first region and a second region of a first conductivity type separated by a first channel region positioned between the first and second regions; a third region and a fourth region of a second conductivity type separated by a second channel region positioned between the third and fourth regions; and a floating gate common to the first and second channel regions; a first interconnect in electrical contact with the first region of the first conductivity type; and a second interconnect in electrical contact with the second region of the first conductivity type. The device may further include a third interconnect in electrical contact with the third region of the second conductivity type; and a fourth interconnect in electrical contact with the fourth region of the fourth conductivity type. The device may further include an injector, the injector comprising a region wherein the common floating gate penetrates into at least one of the first or second channel regions. In some configurations, the semiconductor material further comprises silicon. In some configurations, the insulating substrate further comprises sapphire. In some configurations, the insulating substrate further comprises a layer of silicon dioxide.
In an eighth aspect, the present invention is a semiconductor content addressable memory cell (CAM) device comprising: a first EEPROM cell formed on a first island of semiconductor material on an insulating substrate wherein the first EEPROM cell further comprises: a first EEPROM cell N-channel device which includes a first N+ region and a second N+ region separated by a first channel region positioned between the first and second N+ regions; a first EEPROM cell P-channel device which includes a first P+ region and a second P+ region separated by a second channel region positioned between the first and second P+ regions; a second EEPROM cell formed on a second island of semiconductor material on the insulating substrate wherein the second EEPROM cell further comprises: a second EEPROM cell N-channel device which includes a third N+ region and a fourth N+ region separated by a third channel region positioned between the third and fourth N+ regions; a second EEPROM cell P-channel device which includes a third P+ region and a fourth P+ region separated by a fourth channel region positioned between the third and fourth P+ regions; a common floating gate positioned adjacent the first, second, third and fourth channel regions; a first interconnect in electrical contact with the first N+ region on the first EEPROM cell and the third P+ region on the second EEPROM cell; a first P-channel transistor having a first P-channel transistor source contact biased at a voltage VDD, a first P-channel transistor drain contact connected to the first interconnect, and a clock signal connected to a first P-channel transistor gate contact; a second P-channel transistor having a second P-channel transistor source contact connected to the fourth P+ region on the second EEPROM cell, a second P-channel transistor drain contact, biased at VSS and a first input connected to a second P-channel transistor gate contact; and a first N-channel transistor having a first N-channel transistor drain contact connected to the second N+ region on the first EEPROM cell, a first N-channel transistor source contact connected to the second P-channel transistor drain contact and biased at a voltage VSS, and a second input connected to a first N-channel transistor gate contact. The device may further include an injector, the injector comprising a region wherein the common floating gate penetrates into one or more of the first, second, third or fourth channel regions. In some configurations, the semiconductor material further comprises silicon. In some configurations, the insulating substrate further comprises sapphire. In some configurations, the insulating substrate further comprises a layer of silicon dioxide.
In a ninth aspect, the present invention is a semiconductor device comprising a first island of semiconductor material on an insulating substrate wherein the first island of semiconductor material further comprises: a first region and a second region of a first conductivity type separated by a first channel region positioned between the first and second regions; and a third region and a fourth region of a second conductivity type separated by a second channel region positioned between the third and fourth regions. The device may further include a floating gate positioned over at least a portion of each of the first and second channel regions. In some configurations, a portion of each of the first and second channel regions coincide. The device may further include an inverter configured as a latching sense amplifier, the inverter comprising: a second island of semiconductor material on the insulating substrate wherein the second island of semiconductor material further comprises a fifth region and a sixth region of the first conductivity type separated by a third channel region positioned between the fifth and sixth regions; and a third island of semiconductor material on the insulating substrate wherein the third island of semiconductor material further comprises a seventh region and an eighth region of the second conductivity type separated by a fourth channel region positioned between the seventh region and eighth regions, wherein a voltage Vss is applied to the fifth region of first conductivity type, a voltage Vdd is applied to the seventh region of second conductivity type, and the sixth region of first conductivity type and the eighth region of second conductivity type are interconnected as an output for the latching sense amplifier; wherein the floating gate is positioned over at least a portion of each of the first, second, third and fourth channel regions. The device may further include an injector, the injector comprising a region wherein the floating gate penetrates into one or more of the first or second channel regions. In some configurations, the semiconductor material further comprises silicon. In some configurations, the insulating substrate further comprises sapphire. In some configurations, the insulating substrate further comprises silicon dioxide.
In a tenth aspect, the present invention is a semiconductor device comprising: an island of semiconductor material on an insulating substrate; a first electronic device of a first conductivity type fabricated in the island of semiconductor material, the first electronic device comprising: a first device source region; a first device drain region; and a first device channel region positioned between the first device source region and the first device drain region; and a second electronic device of a second conductivity type fabricated in the island of semiconductor material, the second electronic device comprising: a second device source region; a second device drain region; and a second device channel region positioned between the second device source region and the second device drain region. The device may further include a floating gate positioned over at least a portion of each of the first device channel region and the second device channel region. In some configurations, a portion of each of the first device channel region and the second device channel region coincide. The device may further include an injector, the injector comprising a region wherein the floating gate penetrates into one or more of the first device channel region or the second device channel region. In some configurations, the semiconductor material further comprises silicon. In some configurations, the insulating substrate further comprises sapphire. In some configurations, the insulating substrate further comprises silicon dioxide.
In an eleventh aspect, the present invention is a method for fabricating a semiconductor device which comprises providing a first island of semiconductor material on an insulating substrate wherein the first island of semiconductor material further comprises: a first region and a second region of a first conductivity type separated by a first channel region positioned between the first and second regions; and a third region and a fourth region of a second conductivity type separated by a second channel region positioned between the third and fourth regions. The method may further include providing a floating gate positioned over at least a portion of each of the first and second channel regions. The method may further include providing that a portion of each of the first and second channel regions coincide. The method may further include providing an injector, the injector comprising a region wherein the floating gate penetrates into one or more of the first or second channel regions. In some applications, the method further includes providing that the semiconductor material further comprises silicon. In some applications, the method further includes providing that the insulating substrate further comprises sapphire. In some applications, the method further includes providing that the insulating substrate further comprises silicon dioxide.
In a twelfth aspect, the present invention is a semiconductor device comprising: a layer of semiconductor material on an insulating substrate; a first electronic device of a first conductivity type fabricated in the layer of semiconductor material, the first electronic device comprising a first region and a second region of the first conductivity type separated by a first channel region positioned between the first and second regions; a second electronic device of a second conductivity type fabricated in the layer of semiconductor material, the second electronic device comprising a third region and a fourth region of the second conductivity type separated by a second channel region positioned between the third and fourth regions; and a common floating gate positioned over at least a portion of each of the first and second channel regions. The device may further include an injector, the injector comprising a region wherein the common floating gate penetrates into at least one of the first or second channel regions. In some configurations, the semiconductor material further comprises silicon. In some configurations, the insulating substrate further comprises sapphire. In some configurations, the insulating substrate further comprises silicon dioxide. In some configurations, the first electronic device of the first conductivity type is fabricated in a first island of semiconductor material on the insulating substrate and the second electronic device of the second conductivity type is fabricated in a second island of semiconductor material on the insulating substrate. In some configurations, the first electronic device of the first conductivity type and the second electronic device of the second conductivity type are fabricated in a single island of semiconductor material on the insulating substrate.
In a thirteenth aspect, the present invention is a method for fabricating a semiconductor device which comprises: providing a layer of semiconductor material on an insulating substrate; fabricating in the layer of semiconductor material a first electronic device of a first conductivity type, the first electronic device comprising a first region and a second region of the first conductivity type separated by a first channel region positioned between the first and second regions; fabricating in the layer of semiconductor material a second electronic device of a second conductivity type, the second electronic device comprising a third region and a fourth region of the second conductivity type separated by a second channel region positioned between the third and fourth regions; and a common floating gate positioned over at least a portion of each of the first and second channel regions. The method may further include providing an injector, the injector comprising a region wherein the common floating gate penetrates into at least one of the first or second channel regions. The method may further include providing that the semiconductor material further comprises silicon. The method may further include providing that the insulating substrate further comprises sapphire. The method may further include providing that the insulating substrate further comprises silicon dioxide. The method may further include fabricating the first electronic device of the first conductivity type in a first island of semiconductor material on the insulating substrate and fabricating the second electronic device of the second conductivity type in a second island of semiconductor material on the insulating substrate. The method may further include fabricating the first electronic device of the first conductivity type and the second electronic device of the second conductivity type in a single island of semiconductor material on the insulating substrate.